1. Technical Field
The present disclosure relates to an organic light emitting diode display device, and more particularly, to an organic light emitting diode display device where an electrode of a light emitting diode and an auxiliary line are connected to each other through an emission assisting layer and a method of fabricating the organic light emitting diode display device.
2. Discussion of the Related Art
Among various flat panel displays (FPDs), an organic light emitting diode (OLED) display device has properties such as high luminance and low driving voltage. The OLED display device uses an emissive electroluminescent layer to realize a high contrast ratio and a thin profile, and is excellent at displaying a moving image because of a short response time of several micro seconds (μsec). Also, the OLED display device has no limitation on a viewing angle and is stable even in a low temperature. Since the OLED display device is typically driven by a low voltage (e.g., between 5V and 15V in direct current (DC)), fabrication and design of a driving circuit is easy. Further, a fabrication process for the OLED display device including a deposition and an encapsulation is simple.
The OLED display device may be classified into a top emission type and a bottom emission type according to a light emission direction. The top emission type OLED display device having an advantage in an aperture ratio has been researched and developed as a product having a large size and a high resolution.
FIG. 1 is a cross-sectional view showing an organic light emitting diode display device according to a related art.
In FIG. 1, the OLED display device 10 according to the related art includes a substrate 20 and a thin film transistor (TFT) Td and a light emitting diode (LED) De in each pixel region P on the substrate 20.
A semiconductor layer 22 is formed on the substrate 20, and a gate insulating layer 24 is formed on the semiconductor layer 22. The semiconductor layer 22 includes an active region of an intrinsic semiconductor material at a central portion and source and drain regions of an impurity-doped semiconductor material at both sides of the central portion.
A gate electrode 26 is formed on the gate insulating layer 24 over the semiconductor layer 22, and an interlayer insulating layer 28 is formed on the gate electrode 26. The interlayer insulating layer 28 and the gate insulating layer 24 include first and second contact holes exposing the source and drain regions, respectively, of the semiconductor layer 22.
Source and drain electrodes 30 and 32 spaced apart from each other are formed on the interlayer insulating layer 28 corresponding to the semiconductor layer 22. The source and drain electrodes 30 and 32 are connected to the source and drain regions of the semiconductor layer 22 through the first and second contact holes, respectively.
The semiconductor layer 22, the gate electrode 26, the source electrode 30 and the drain electrode 32 constitute a thin film transistor (TFT) Td. A passivation layer 34 is formed on the TFT Td and has a third contact hole exposing the source electrode 30.
A first electrode 36 is formed on the passivation layer 34 corresponding to a central portion of the pixel region P and is connected to the source electrode 30 through the third contact hole.
A bank layer 38 is formed on the first electrode 36. The bank layer 38 covers an edge portion of the first electrode 36 and has an opening exposing a central portion of the first electrode 36.
A first emission assisting layer 40 is formed on the first electrode 36 exposed through the opening of the bank layer 38, and an emitting layer 42 is formed on the first emission assisting layer 40 in the opening of the bank layer 38. In one aspect, the first emission assisting layer 40 assists injection or transport of carriers (e.g., holes or electrons).
A second emission assisting layer 44 is formed on the entire surface of the substrate 20 having the emitting layer, and a second electrode 46 is formed on the entire surface of the substrate 20 having the second emission assisting layer 44. In one aspect, the second emission assisting layer 44 assists injection or transport of other carriers (e.g., electrons or holes).
The first emission assisting layer 40 may include a hole injecting layer (HIL) and a hole transporting layer (HTL), and the second emission assisting layer 44 may include an electron injecting layer (EIL) and an electron transporting layer (ETL). The first electrode 36, the first emission assisting layer 40, the emitting layer 42, the second emission assisting layer 44 and the second electrode 46 constitute a light emitting diode De.
In the OLED display device 10, the second emission assisting layer 44 is not patterned in each pixel region P. Instead, the second emission assisting layer 44 is formed on the entire surface of the substrate 20 for cost reduction of and yield increase due to process simplification in a product having a large size and a high resolution.
In addition, since the second electrode 46 should have transparency in the top emission type OLED display device 10, the second electrode 46 may be formed by depositing a metallic material such as aluminum (Al), magnesium (Mg) and silver (Ag) with a relatively thin thickness. However, a resistance of the second electrode 46 increases due to the relatively thin thickness and non-uniformity in brightness is caused by a voltage drop of a low level voltage VSS.
To prevent the non-uniformity in brightness, a structure where the second electrode 46 is connected to an auxiliary electrode or an auxiliary line of a low resistance material at a border of the pixel region P under the emitting layer 42 has been suggested.
In the product having a large size with a high resolution, however, since second emission assisting layer 44 is formed on the entire surface of the substrate 20, it is required to eliminate the second emission assisting layer 44 on the auxiliary electrode or the auxiliary line for connecting the second electrode 46 to the auxiliary electrode or the auxiliary line.
Accordingly, a laser patterning and a patterning using a separator have been suggested as a method of eliminating the second emission assisting layer 44 on the auxiliary electrode or the auxiliary line.
However, for laser patterning, a step of irradiating a laser beam onto the second emission assisting layer 44 on the auxiliary electrode or the auxiliary line is added, therefore a fabrication cost increases and a yield decreases. Similarly, for patterning using the separator, a step of forming the separator is added, thus a fabrication cost increases and a yield decreases. Further, the emitting layer 42 can be deteriorated due to a sputtering for forming a transparent conductive layer as an uppermost layer.